1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the semiconductor device, or more specifically to a flip-chip mounted semiconductor device.
2. Description of the Related Art
Semiconductor devices have been made smaller in size, highly functional, and highly efficient recently. Accordingly, power consumption of the devices has been increasing. This increase is attributable to longer loops of bonding wires and to deterioration in electric properties associated with an increase in the number of electrodes along an increase in the number or signals, i.e. an increase in the number of wires, for example.
Flip-chip mounting, widely known as a technique for dealing with the above-mentioned problem, is a method of mounting a chip on a substrate in the following manner. A substrate has, on a surface thereof, a stud bump having a pointed top and made of high melting point metal. A semiconductor chip has a solder bump formed on an electrode on a surface thereof. Here, the stud bump is inserted into the solder bump which is melted by heating in a range from 300° C. to 400° C. Then a pressure is applied to the semiconductor chip so as to squash the stud bump in order to obtain a desired interval between the substrate and the semiconductor chip (Japanese Patent Application Publication No. 2007-43010).
In this mounting method, the stud bump is squashed when the semiconductor chip is mounted. This leads to a problem that the pressure applied during this mounting operation damages a wiring layer formed below the electrode on the surface of the semiconductor chip, and an insulating film located between the electrode and the wiring layer. Moreover, the heat generated during the mounting operation also damages the wiring layer and the insulating film between the electrode and the wiring layer. The damages thus caused on the wiring layer and the insulating film generate a leak current that leads to deterioration in electric properties of the device. Considering that numerous wiring layers are usually formed at the central part of a semiconductor chip, the above-mentioned flip-chip mounting has difficulty in forming the electrodes at the central part of the semiconductor chip.
The fact that the electrodes can not be formed at the central part of the semiconductor chip as in the above case, along with the recent size reduction of the semiconductor chips, leads to deterioration in the electric properties. Specifically, when the above-described flip-chip mounting method is employed, electrodes are only allowed to be formed at an outer peripheral part of a semiconductor chip. Therefore, power source electrodes are also allowed to be formed only at the outer peripheral part. However, reduction in chip size reduces the width of silicon wiring that connects the power source electrodes and a semiconductor element formed at the central part of the chip. Accordingly, resistance of the silicon wiring increases and a voltage drop occurs as a consequence. Therefore, when the power source electrodes are formed at the outer peripheral part of the semiconductor element, a voltage to be supplied to the semiconductor element is below a voltage fed to a power source due to the voltage drop attributable to the silicon wiring. This leads to a problem of deterioration in the electric properties of the semiconductor chip as a whole.
Here, there is known a substrate having power source electrodes arranged in a lattice fashion on a surface at a central part and having signal electrodes arranged in a lattice fashion on an overall surface in the periphery of these power source electrodes located at the central part (Japanese Patent Application Publication No. 2000-307005).
However, the above-described substrate is for a semiconductor device under a standard where solder balls are formed entirely on a back surface in a lattice fashion. The substrate for the semiconductor device under such a standard requires numerous electrodes on the surface of the substrate, numerous solder balls to be formed on the entire back surface thereof, and numerous wiring layers to form wiring for establishing connection among the electrodes and the solder balls. Hence this configuration has a problem of high costs for manufacturing the substrate. Moreover, the power source electrodes to be formed at the central part of this substrate are connected to the respective solder balls on the back surface through respective through-holes formed immediately below the electrodes. Accordingly, there is also a problem of design restriction for the wiring to be formed on the respective wiring layers.
That is to say, according to the related arts of semiconductor devices each obtained by flip-chip mounting a semiconductor chip on a substrate, the substrate and the semiconductor chip are designed with low freedom and a semiconductor device having excellent electric properties is hardly achieved.